Semiconductor transistors, in particular field-effect controlled switching devices such as a Metal Oxide Semiconductor Field-effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT) have been used for various applications including but not limited to use as switches in power supplies and power converters, electric cars, air-conditioners, and even stereo systems. Particularly with regard to power devices capable of switching large currents and/or operating at higher voltages, low on-state resistance, which is in the following also referred to as on-resistance Ron, and high voltage blocking capability are often desired. Due to structural efficiency and low on-resistance Ron, vertical trench MOSFETs are widely used, in particular in power applications. The breakdown voltage of trench MOSFETs may be raised by optimizing the shape and depth of the trench and in particular by arranging an insulated field electrode in the vertical trench below the insulated gate electrode of the trench MOSFET. The field electrode is typically connected to source potential and insulated from drain potential by a field oxide. Accordingly, charges in the drift region between two neighboring vertical trenches are at least partially compensated and thus the blocking capability improved. Typically, the blocking capability of such a MOSFET increases with the vertical extension of the trench and the thickness of the field oxide. However, internal mechanical stress resulting from tensions at the corresponding semiconductor-insulator interfaces typically also increases with the vertical extension of the trench and the field oxide thickness, respectively. This may result in a bowing of the semiconductor substrate of the MOSFET, in particular during manufacturing on wafer level.
Another configuration of a vertical trench MOSFET is the so-called TEDFET (Trench Extended Drain Field-Effect Transistor) which allows for an improved decoupling of voltage blocking capability and on-resistance Ron compared to conventional MOSFETs by controlling the conductivity in the drift region by a drift control region which is separated from the drift region by an accumulation dielectric vertically extending along the drift region. Power TEDFETS of higher blocking capability utilize an accumulation dielectric that extends deeply into the semiconductor material and may result in mechanical stress levels that may have an impact on manufacturing.
To reduce wafer bowing during device manufacturing, the thickness of the wafer may be increased, for example by providing an additional epitaxial layer below the vertical trench. However, this increases costs and may increase on-resistance Ron. Alternatively or in addition, pre-stressed layers may be applied on the back-side of the wafer during device manufacturing. However, this also increases costs. Furthermore, different compressive and tensile layers may be required during different process steps to compensate the bowing. Even further, compensating the wafer bowing typically increases mechanical stress in the wafer. Accordingly, risk of forming crystal defects during epitaxial processes increases. This may even have an impact on the device performance.
Accordingly, there is a need to provide mechanical stress reduced vertical MOSFETs and related manufacturing methods.